High performance Parallel Linear Sorter Core Design

Hardware sorters exploit inherent concurrency to improve the performance of sequential, softwarebased sorting algorithms. They are often based on Batcher’s odd-even or bitonic merging networks to attenuate the areagreedy hardware solutions. In this paper, a new hardware sorter architecture is presented. It is composed of smaller sorter circuits inspired on insertion sorting algorithms that contain as many data-slice cells as data to sort. Such sorters are easily scalable and require minimal control schemes. We outline the properties of the sorter modules in order to introduce some architectures that overcome their limitations. Such architectures are based on combining several of such sorters in parallel to speed up the computing of the final result. Different area and speed requirements lead to a variety of architectural considerations that produce optimal designs for each case. An application of such sorters designs is presented and implemented on FPGAs. The synthesis results are compared with other parallel sorting architectures.